Voltage comparator

ABSTRACT

In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of French Patent Application No.1911934, filed on Oct. 24, 2019, which application is herebyincorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to an electronic system andmethod, and, in particular embodiments, to a voltage comparator.

BACKGROUND

Voltage comparators are provided in many electronic circuits. In anelectronic circuit comprising a voltage comparator, the state of itsbinary output signal may condition the implementation of a step or of acontrol.

For example, a voltage comparator is generally provided in aswitched-mode voltage converter where a voltage for powering theconverter is chopped by the switching of switches to implement phases ofpower storage in an inductance or inductive element and phases ofdelivery, to a load connected to the converter output, of the powerstored in the inductance. The implementation of a switching of at leastone of the converter switches is then conditioned by the binary state ofthe comparator output signal.

Known voltage comparators have various disadvantages, which may inparticular result in malfunctions of the voltage converters comprisingsuch known voltage comparators.

SUMMARY

Some embodiments relate voltage comparators configured to deliver abinary signal having a state representative of the comparison betweentwo voltages received by two respective inputs of the comparator.

An embodiment overcomes all or part of the disadvantages of knownvoltage comparators.

An embodiment provides a voltage comparator comprising:

a first switch having a conduction terminal connected to an internalnode;

a current source;

a capacitor; and

a second switch connected in parallel with the capacitor,

wherein the current source, the capacitor, and the first switch areseries-connected.

According to an embodiment, a terminal of the current source is coupled,preferably connected, to the capacitor, another terminal of the currentsource being coupled, preferably connected, to a first node ofapplication of a first DC potential.

According to an embodiment, when a variation of the potential of theinternal node towards the first potential causes a switching of anoutput of the comparator, the first switch is configured to turn on andthe second switch is configured to turn off after the turning-on of thefirst switch.

According to an embodiment, the comparator further comprises a firstinverter having an input coupled, preferably connected, to the internalnode and having an output controlling the first switch.

According to an embodiment, the first inverter is configured to controla turning on of the first switch after the variation of the potential ofthe internal node.

According to an embodiment, the comparator further comprises a secondinverter having an input coupled to the internal node and having anoutput coupled, preferably connected, to the output of the comparatorand controlling the second switch.

According to an embodiment, the second inverter is configured to controla turning off of the second switch after the variation of the potentialof the internal node.

According to an embodiment, the comparator comprises at least twoinverters in series between the internal node and the output of thecomparator, the second inverter forming part of the at least twoinverters.

According to an embodiment, the first inverter forms part of the atleast two inverters.

According to an embodiment, the comparator further comprises first andsecond transistors in series between the first node and a second node ofapplication of a second DC potential, the comparator being configured toreceive a power supply voltage between the first and second nodes andthe first and second transistors being connected to each other at thelevel of the internal node.

According to an embodiment, the first potential is a referencepotential, the first and second switches being implemented by NMOStransistors.

According to an embodiment, the first potential is a power supplypotential, the first and second switches being implemented by PMOStransistors.

According to an embodiment, the potential of the internal node isrepresentative of the comparison between two voltages to be comparedapplied to two respective inputs of the comparator.

Another embodiment provides a voltage converter comprising a comparatorsuch as described.

According to an embodiment, the comparator is configured to compare anoutput voltage of the converter with a set point voltage of theconverter.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages will be discussed indetail in the following non-limiting description of specific embodimentsin connection with the accompanying drawings.

FIG. 1 very schematically shows an example of a voltage converter of thetype to which the described embodiments apply;

FIG. 2 shows timing diagrams illustrating a desired operation of theconverter of FIG. 1 , according to an embodiment;

FIG. 3 partially and schematically shows an embodiment of a voltagecomparator;

FIG. 4 partially and schematically shows an embodiment of a voltagecomparator; and

FIG. 5 shows timing diagrams illustrating the operation of thecomparator of FIG. 4 , according to an embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The same elements have been designated with the same reference numeralsin the different drawings. In particular, the structural and/orfunctional elements common to the different embodiments may bedesignated with the same reference numerals and may have identicalstructural, dimensional, and material properties.

For clarity, only those steps and elements which are useful to theunderstanding of the described embodiments have been shown and aredetailed. In particular, the various usual electronic circuits,particularly integrated, where a voltage comparator may be provided,have not been detailed, the described embodiments being compatible withsuch usual circuits.

Throughout the present disclosure, unless otherwise specified, the term“connected” is used to designate a direct electrical connection betweencircuit elements, whereas the term “coupled” is used to designate anelectrical connection between circuit elements that may be direct, ormay be via one or more other elements.

In the following description, when reference is made to terms qualifyingabsolute positions, such as terms “front,” “back,” “top,” “bottom,”“left,” “right,” etc., or relative positions, such as terms “above,”“under,” “upper,” “lower,” etc., or to terms qualifying directions, suchas terms “horizontal,” “vertical,” etc., unless otherwise specified, itis referred to the orientation of the drawings.

Unless otherwise specified, the terms “about,” “approximately,”“substantially,” and “in the order of,” are used herein to designate atolerance of plus or minus 10%, preferably of plus or minus 5%, of thevalue in question.

In the following description, when reference is made to the voltage of anode or of a terminal, it is considered that it is, unless otherwiseindicated, the voltage between the point or node and a referencepotential, typically the ground. Further, when reference is made to thepotential of a node or of a terminal, it is considered that thispotential is, unless otherwise indicated, referenced to the referencepotential. The voltage and the potential of a given node or of a giventerminal will further be designated with a same reference.

In the following description, a signal which alternates between a firstconstant state, for example, a low state, noted “0,” and a secondconstant state, for example, a high state, noted “1,” is called a“binary signal.” The high and low states of different binary signals ofa same electronic circuit may be different. In particular, the high andlow states of binary signals may correspond to voltages or to currentswhich may not be perfectly constant in the high or low state.

FIG. 1 very schematically shows an example of a voltage converter 1 ofthe type to which the described embodiments apply. In this example,converter 1 is a DC/DC converter, which converts a DC power supplyvoltage into a DC output voltage. In this example, converter 1 is ofbuck type, that is, the DC output voltage delivered by converter 1 has alower value than its DC power supply voltage.

Converter 1 is configured to deliver a DC output voltage VOUT on anoutput node 2.

Converter 1 is powered with a DC power supply voltage Vbat. Converter 1is connected between a conductive rail or node 3 configured to receivevoltage Vbat or, in other words, DC potential Vbat, and a conductiverail or node 5 configured to receive a reference potential, typicallyground GND.

Converter 1 is configured to deliver voltage Vout equal to a set pointvalue. For this purpose, converter 1 receives, on an input node 7, a DCset point voltage Vref, having its value, in the present example, equalto the set point value of voltage Vout.

In this example, voltages Vout, Vbat, and Vref are positive.

Converter 1 comprises a first MOS transistor 9, preferably a PMOStransistor. MOS transistor 9 is connected between node 3 and a node 11.In other words, a first conduction terminal of transistor 9, forexample, its source, is connected to rail 3, a second conductionterminal of transistor 9, for example, its drain, being connected tonode 11.

Converter 1 further comprises a second MOS transistor 13, preferably anNMOS transistor. Transistor 13 is connected between node 11 and rail 5.In other words, a first conduction terminal of transistor 13, forexample, its source, is connected to rail 5, a second conductionterminal of transistor 9, for example, its drain, being connected tonode 11.

Thus, transistors 9 and 13 are series-connected between rails 3 and 5and are connected to each other at the level of internal node 11.

Converter 1 comprises an inductive element or inductance 15. Inductance15 is connected between node 11 and node 2.

Converter 1 comprises a voltage comparator 17. Voltage comparator 17 isconfigured to deliver a binary signal START representative of thecomparison of voltage Vout with voltage Vref. In other words, comparator17 is configured to deliver signal START in a first binary state ifvoltage Vout is greater than voltage Vref, and in a second binary stateif voltage Vout is lower than voltage Vref. For this purpose, comparator17 comprises a first input configured to receive voltage Vref, the firstinput here being connected to node 7, and a second input configured toreceive voltage Vout, the second input here being connected to node 2.An output of comparator 17 delivers signal START.

The case where the first binary state of signal START corresponds to ahigh state of signal START and the second binary state of signal STARTcorresponds to a low state of signal START is considered herein as anexample. Voltage Vref is then received by the inverting input (−) ofcomparator 17 and voltage Vout is received by the non-inverting input(+) of comparator 17.

Although this is not shown in FIG. 1 , comparator 17 is here poweredwith power supply voltage Vbat. Thus, comparator 17 comprises a node (ora terminal) connected to node 3 and a node (or a terminal) connected tonode 5 to receive voltage Vbat. In the high state, voltage or signalSTART has a value substantially equal to that of voltage Vbat and, inthe low state, voltage or signal START has a substantially zero value(ground).

Converter 1 comprises a control circuit 19. Circuit 19 is configured toimplement or control the operating cycles of converter 1 to regulatevoltage Vout to its set point value Vref (or based on voltage Vref).

For this purpose, circuit 19 comprises:

a terminal 191 coupled, preferably connected, to the output comparator17, terminal 191 being configured to receive signal START;

terminals 192 and 193 coupled, preferably connected, to respective nodes3 and 5 to receive power supply voltage Vbat;

a terminal 194 coupled, preferably connected, to a control terminal, orgate, of transistor 9; and

a terminal 195 coupled, preferably connected, to a control terminal orgate of transistor 13.

Converter 1 comprises an output capacitor (not shown) connected betweennodes 2 and 5. As an example, the capacitance is in the order of from2.2 μF to 20 μF, or even more. Such an output capacitor plays the roleof a filter. In other words, the converter output capacitor enables tosmooth the current present on node 2 and to store power supplied to node2 by the converter.

Although this is not shown herein, in operation, a load is connectedbetween nodes 2 and 5 to be powered with potential Vout.

In the present example, converter 1 is configured to operate in pulsefrequency modulation. Circuit 19 is then configured to start anoperating cycle of converter 1 when voltage Vout is lower than voltageVref and both transistors 9 and 13 are in the off state. Moreparticularly, at the beginning of each operating cycle, while the twotransistors 9 and 13 are in the off state and no current IL flowsthrough inductance 15, circuit 19 is configured to control the settingto the on state of transistor 9, transistor 11 being left in the offstate. Power is then stored in inductance 15 during a first time periodwhen transistor 9 is maintained in the on state by circuit 19. At theend of this first time period, circuit 19 is configured to control thesetting to the off state of transistor 9 and the setting to the on stateof transistor 13. Power is then delivered back by inductance 15 to theload connected at the converter output, during a second time period whentransistor 13 is maintained in the on state by circuit 19. At the end ofthis second time period, circuit 19 is configured to control the settingto the off state of transistor 13.

Signal START being representative of the fact that voltage Vout is ornot lower than voltage Vref, output signal START of comparator 17conditions the starting of an operating cycle of converter 1.

FIG. 2 shows timing diagrams illustrating the desired operation of theconverter 1 of FIG. 1 .

The timing diagram at the top of FIG. 2 illustrates the variation overtime t of voltage Vout, in volts V. The timing diagram at the bottom ofFIG. 2 illustrates the corresponding variation, over time t, of thecurrent IL flowing through inductance 15.

At a time t0, transistors 9 and 13 are in the off state, current IL iszero, and voltage Vout is greater than voltage Vref. Although this isnot illustrated herein, signal START then is in the first binary state,the high state in the present example.

Between time t0 and a subsequent time t2, voltage Vout decreases, forexample, due to the fact that the load connected to converter 1 consumescurrent.

At a time t1 between times t0 and t2, voltage Vout becomes smaller thanvoltage Vref. Although this is not shown in FIG. 2 , as a result,between times t1 and t2, output START of comparator 17 switches form thefirst binary state to the second binary state, that is, the low state inthe present example. As a response to such a switching of signal START,circuit 19 controls the setting to the on state of transistor 9,transistor 9 turning on at time t2.

From time t2, inductance 15 has a terminal connected to node 2 and aterminal coupled to rail 3, via transistor 9, and the current IL flowingthrough inductance 15 increases until a time t4 subsequent to time t2.Thus, between times t2 and t4, voltage Vout increases. In particular,voltage Vout becomes greater again than voltage Vref at a time t3 in therange from times t2 and t4 and, although this is not shown in FIG. 2 ,this results in output START of comparator 17 switching from the secondbinary state to the first binary state.

At time t4, circuit 19 controls the setting to the on state oftransistor 13 and the setting to the off state of transistor 9.

From time t4 and until a time t5 subsequent to time t4, inductance 15has a terminal connected to node 2 and a terminal coupled to rail 5, viatransistor 13. Current IL flowing through inductance 15 decreases. Aslong as current IL is not zero, voltage Vout keeps on increasing if thecurrent drawn by the load is lower than the current IL delivered to node2.

At time t5, the current IL in inductance 15 becomes zero and circuit 19controls the setting to the off state of transistor 13. From this time,voltage Vout decreases, similarly to what happened at time t0.

Although this is not shown herein, if voltage Vout falls back belowvoltage Vref at a time subsequent to time t5, output START switches backto its second binary state and, as a response to this switching, circuit19 implements a new operating cycle such as described in relation withtimes t2, t4, and t5.

FIG. 3 partially and schematically shows an embodiment of voltagecomparator 17.

Comparator 17 comprises a PMOS transistor 301 and an NMOS transistor 303series-connected between a node 305 configured to receive a referencepotential and a node 307 configured to receive a power supply potential.In other words, comparator 17 is configured to receive a power supplyvoltage between nodes 305 and 307. In this example, comparator 17 ispowered with voltage Vbat, node 305 being coupled, preferably connected,to node 5 and node 307 being coupled, preferably connected, to node 3.

Transistors 301 and 303 are connected to each other at the level of anintermediate node 309 of comparator 17. More particularly, the source oftransistor 301 is coupled, preferably connected, to node 307, the sourceof transistor 303 is coupled, preferably connected, to node 305 and thedrains of transistors 301 and 303 are both coupled, preferablyconnected, to node 309.

Transistors 301 and 303 form an output stage of comparator 17.

Comparator 17 is configured so that the potential of node 309 isrepresentative of the comparison between the two voltages compared bycomparator 17, that is, voltages Vref and Vout in the present example.More precisely, comparator 17 is configured to control transistors 301and 303 based on the difference between the voltages to be compared thatit receives, whereby the potential of node 309 is representative of thecomparison of the voltages to be compared received by comparator 17.

For example, when the voltage received by the first input of comparator17, for example, the voltage Vref received by the inverting input, isgreater than that received by the second input of comparator 17, forexample, the voltage Vout received by the non-inverting input,transistors 301 and 303 are controlled so that the current delivered tonode 309 via transistor 301 is lower than the current drawn from node309 by transistor 303, whereby the potential of node 309 is drawntowards the potential of node 305. Conversely, when the voltage receivedby the first input is lower than that received by the second input,transistors 301 and 303 are controlled so that the current supplied tonode 309 via transistor 301 is greater than the current drawn from node309 by transistor 303, whereby the potential of node 309 is pulledtowards the potential of node 307.

Comparator 17 further comprises a gain stage, coupling the internal node309 of output stage 301, 303 of the comparator to an output, or outputnode or terminal 311 of comparator 17. The gain stage comprises aplurality of inverters in series between node 309 and output 311. Inthis example, the comparator output is configured to deliver signalSTART.

In the shown example, the comparator comprises, from node 309 to node311, four inverters, respectively I1, I2, I3, and I4. The input ofinverter I1 is connected to node 309, its output being connected to theinput of inverter I2. The input of inverter I3 is connected to theoutput of inverter I2, the output of inverter I3 being connected to theinput of inverter I4. The output of inverter I4 is connected to output311 of the comparator.

Thus, according to the potential of node 309, the output of inverter I1is in the high state or in the low state, whereby signal START isrespectively in the low state or in the high state.

Taking the above example, when the potential of node 309 is pulledtowards the potential of node 305 and becomes smaller than a switchingthreshold of inverter I1, the output thereof switches to the high state,which causes the switching to the low state of signal START. Conversely,when the potential of node 309 is pulled towards the potential of node307 and becomes greater than a switching threshold of inverter I1, theoutput thereof switches to the low state, which causes the switching tothe high state of signal START.

However, in practice comparator 17 may cause a malfunction of converter1. Indeed, referring again to the timing diagrams of FIG. 2 , whenvoltage Vout becomes equal to and then smaller than voltage Vref at timet1, the potential of node 309, then greater than the switching thresholdof inverter I1, decreases to become lower than the switching thresholdof inverter I1. This causes the switching to the high state of theoutput of inverter I1 and, after the propagation of this switchingthrough inverters I2, I3, and I4, the switching to the low state ofoutput signal START of comparator 17. During such switchings of theinverters of the gain stage of comparator 17, current is drawn fromnodes 305 and 307, and thus respectively from nodes 5 and 3. Thisparticularly results in unwanted variations of the potential GND presenton node 3, linked to the parasitic resistance on potential GND or, inother words, linked to the parasitic resistance of rail 5 at potentialGND. Such unwanted variations of potential GND result in unwantedvariations of voltage Vout. Such unwanted variations of voltage Vout mayresult in voltage Vout becoming greater again than voltage Vref at thetime of the switching of the output of inverter I1 to the high state.When, due to such unwanted variations of voltage Vout, the latterbecomes greater again than voltage Vref, the potential of node 309 isthen pulled towards the potential of node 307 and may become greateragain than the switching threshold of inverter I1. If this occurs, theoutput of inverter I1 switches to the low state, which results in outputSTART switching to the high state, which is not desirable. Moregenerally, output START of comparator 17 may start oscillating, which isnot desirable. Indeed, the first switching(s) to the low state of signalSTART may for example be too short to be detected by circuit 19, whichthus triggers no operating cycle. This results in a delay in theimplementation of a phase of power storage in inductance 15, and thus ina poor regulation of voltage Vout.

To prevent such oscillations of signal START, it could have been devisedto replace comparator 17 with a static hysteresis comparator. However,when using a static hysteresis comparator, when voltage Vout decreasesand crosses voltage Vref and signal START switches to the low state, forsignal START to switch to the high state, voltage Vout should becomegreater than voltage Vref plus, or increased by, a fixed or constanthysteresis value. This raises an issue. For example, if, at the end ofan operating cycle of converter 1, voltage Vout has increased from avalue smaller than Vref to a value between Vref and Vref plus thehysteresis value, signal START will not switch to the high state eventhough voltage Vout is greater than voltage Vref. Thus, from as soon asthe end of the operating cycle of converter 1, circuit 19 erroneouslydeduces from the low state of signal START that voltage Vout is stilllower than voltage Vref, and starts a new operating cycle, which ishowever not necessary.

FIG. 4 partially and schematically shows an embodiment of a voltagecomparator 400. Comparator 400 comprises many elements in common withcomparator 17 which will not be detailed again, only the differencesbetween comparators 17 and 400 being here highlighted. The case wherecomparator 400 is used as a comparator 17 of the converter 1 describedin relation with FIG. 1 or, in other words, comparator 400 replacescomparator 17 in converter 1, is here considered as an example.

As compared with comparator 17, comparator 400 comprises a (first)switch 401 having a conduction terminal connected to internal node 309.Comparator 400 further comprises a capacitor, or capacitive element,403, and a current source 405. Switch 401, capacitor 403, and currentsource 405 are series-connected, in this order, between node 309 andnode 305. In other words, another conduction terminal of switch 401 iscoupled, preferably connected, to a terminal or electrode of capacitor403, the other terminal or electrode of capacitor 403 being coupled,preferably connected, to a terminal of current source 405, and the otherterminal of current source 405 being coupled, preferably connected, tonode 305.

Comparator 400 also comprises a (second) switch 407 connected inparallel with capacitor 403. In other words, a conduction terminal ofswitch 407 is connected to a terminal of capacitor 403, the otherconduction terminal of switch 407 being connected to the other terminalof capacitor 403.

In this embodiment where current source 405 is coupled, preferablyconnected, to node 305 at potential GND, switch 401 is configured toturn on when a potential variation of node 309 causes a switching ofsignal START to the low state. Further, as a response to the switchingof signal START to the low state, switch 407 is configured to turn offafter the turning on of switch 401. The turning on of switch 407results, like the turning off of switch 401, from a variation of thepotential of node 309 causing a switching of signal START to the lowstate, that is, here, from a variation of the potential of node 309 tothe potential of node 305 during which the potential of node 309 becomeslower than the switching threshold of inverter I1. Further, currentsource 405 is here configured to draw current from node 309 when switch401 is on and switch 407 is off.

According to an embodiment, switches 401 and 407 are controlled by theoutputs of two inverters of the gain stage of comparator 400. Thus, thecontrol of switches 401 and 407 does not require providing an additionalcontrol circuit with respect to the comparator 17 described in relationwith FIG. 3 .

According to an embodiment, switches 401 and 407 are each implemented bya MOS transistor, for example, NMOS transistors.

According to an embodiment, transistor 401 is controlled by the outputof inverter I1, that is, by an inverter having its input coupled,preferably connected, to node 309. In other words, a control terminal orgate of transistor 401 is coupled, preferably connected, to the outputof inverter I1.

As a variation, transistor 401 is controlled by the output of inverterI3. However, an advantage of controlling transistor 401 with the outputof inverter I1 rather than with the output of inverter I3 is that theturning on of switch 401 occurs sooner after the potential of node 309has become lower than the switching threshold of inverter I1.

According to an embodiment, transistor 407 is controlled by the outputof inverter 14, that is, by an inverter having its output coupled,preferably connected, to output 311 of comparator 400. In other words, acontrol terminal or gate of transistor 407 is coupled, preferablyconnected, to the output of inverter I4.

As a variation, when transistor 401 is controlled by the output ofinverter I1, transistor 407 may be controlled by the output of inverterI2. However, an advantage of controlling transistor 407 with the outputof inverter I4 rather than with the output of inverter I2 is that theturning off of switch 407 only occurs after the switching of signalSTART.

In comparator 400, the turning on of switch 401, while switch 407 is on,enables to pull the potential of node 309 to the potential of node 305having current source 405 coupled thereto. In other words, the turningon of switch 401 enables to confirm the state of node 309 with respectto the switching threshold of inverter I1 (and thus of output 311). Inthis embodiment, the turning on of switch 401 enables to confirm thatthe potential of node 309 is lower than the switching threshold ofinverter I1 or, in other words, to confirm a low state of node 309.Further, current source 405 draws current from node 309 in addition tothe current already drawn from node 309 by transistor 303. This amounts,in practice, to increasing voltage Vref by a hysteresis value defined bythe current drawn from source 405, so that voltage Vout should then begreater than voltage Vref plus the hysteresis value in order for thecomparator output to be able to switch to the high state.

Further, the turning off of switch 407, while switch 401 is on, causesthe beginning of a timing at the end of which the potential of node 309recovers the value that it would have had in the absence of switches 401and 407, of capacitor 403, and of current source 405 or, in other words,at the end of which voltage Vref is no longer increased by thehysteresis value. The duration of such a timing is at least partlydetermined by the load of capacitor 403 or, in other words, by the valueof the current delivered by current source 405 and by the value ofcapacitor 403.

An advantage of increasing voltage Vref by a hysteresis value onlybetween the time when the potential of node 309 becomes lower than theswitching threshold of inverter I1 and the end of thepreviously-described timing is that, in practice, voltage Vout keeps ondecreasing. As a result, at the end of the timing, when the potential ofnode 309 recovers the value that it would have had in the absence ofelements 401, 403, 405, and 407, this value is lower than at the time ofthe switching of the output of inverter I1 to the high state. Further,as long as voltage Vref is increased by the hysteresis value, even ifvoltage Vout varies in unwanted fashion, resulting in voltage Voutbecoming greater than voltage Vref before decreasing back below voltageVref, as long as voltage Vout does not become greater than voltage Vrefplus the hysteresis value, signal START remains in the low state. Ascompared with a static hysteresis comparator where voltage Vref wouldpermanently be increased by a hysteresis value, comparator 400 is adynamic hysteresis comparator when voltage Vref is increased by ahysteresis value only for a certain time period after the switching tothe low state of signal START.

For a given application, it will be within the abilities of thoseskilled in the art to determine the value of the current of currentsource 405 to avoid for an unwanted variation of voltage Vout while thehysteresis is applied to voltage Vref to cause a switching to the lowstate of the output of inverter I1. It will also be within the abilitiesof those skilled in the art to determine the value of the current ofcurrent source 405 and the capacitance value, and thus the duration ofthe timing, particularly so that, when the potential of node 309recovers the value that it would have had in the absence of elements401, 403, 405, and 407, the value of potential 309 is sufficientlydistant from the switching threshold of inverter I1 to avoid for anunwanted variation of voltage Vout to cause a switching to the low stateof the output of inverter I1. In other words, it will be within theabilities of those skilled in the art to determine the value of thecurrent of current source 405 and the capacitance value so that, at theend of the timing, the value of the potential of node 309 is no longerin a critical zone, or critical range of values, where an unwantedvariation of voltage Vout might result in an unwanted switching of theoutput of inverter I1 to the high state.

FIG. 5 shows very simplified timing diagrams illustrating the operationof the comparator 400 of FIG. 4 , in the case where comparator 400replaces the comparator 17 of converter 1 (FIG. 1 ). More particularly,FIG. 5 shows a timing diagram A (at the top of FIG. 5 ) illustrating thevariation over time t of voltage Vout, a timing diagram B (in the middleof FIG. 5 ) illustrating the variation over time t of potential V309 ofnode 309, and a timing diagram C (at the bottom of FIG. 5 ) illustratingthe variation over time t of the output signal START of comparator 400.

At a time t50, voltage Vout is greater than voltage Vref, the potentialV309 of node 309 is greater than the switching threshold Vcom ofinverter I1, and signal START is in the high state. In the presentexample, voltage Vout has been greater than voltage Vref for asufficiently long time for the potential of node 309 to be at a high ormaximum value V1, for example, substantially equal to the potential ofnode 307.

Further, at time t50, switches 401 and 407 are respectively off and on.

At time t50 and after time t50, voltage Vout decreases, for example dueto the current drawn from output node 2 of converter 1 by a load.

At a next time t51, voltage Vout becomes equal to and then smaller thanvoltage Vref. As a result, the current drawn from node 309 by transistor303 becomes greater than the current supplied to node 309 by transistor301, and potential V309 decreases.

At a next time t52, potential V309 becomes equal to and then smallerthan threshold Vcom. The output (not illustrated in FIG. 5 ) of inverterI1 then switches to the high state. This results in the turning on ofswitch 401. In practice, switch 401 turns on after time t52 althoughFIG. 5 shows this turning on at time t52. The turning on of switch 401results in potential V309 being pulled towards the potential of node 305or, in other words, potential V309 is placed at a value V2 lower thanthreshold Vcom. Still in other words, the potential V309 of node 309decreases down to value V2, which is lower than the value that it wouldhave had in the absence of elements 401, 403, 405 and 407. Value V2 ispreferably outside of the critical range of values of potential V309. InFIG. 5 , between time t52 and a subsequent time t55, the value thatpotential V309 would have had in the absence of elements 401, 403, 405,and 407 and of unwanted variations of voltage Vout is shown in dottedlines.

At a next time t53, the switching of the output of inverter I1 haspropagated through inverter chain I2, I3, and I4 all the way to output311 of the comparator, whereby signal START switches to the low state.

Between times t52 and t53, during successive switchings of inverters I1to I4, if the value of voltage Vout varies according to variations ofpotential GND on node 5, and particularly if voltage Vout becomesgreater than voltage Vref, as long as the current drawn from node 309 bysource 405 and transistor 303 remains greater than the current deliveredto node 309 by transistor 301, potential V309 remains substantiallyequal, or even equal to value V2, and thus does not become greater againthan threshold Vcom, conversely to what might occur in the comparator 17described in relation with FIG. 4 . In other words, even if voltage Voutbecomes greater than voltage Vref due to unwanted variations of voltageVout, as long as voltage Vout remains smaller than voltage Vrefincreased by the dynamic hysteresis value, the output of comparator 400remains in the low state. It will be within the abilities of thoseskilled in the art to size, for a given application, current source 405,and thus value V2, to prevent for an unwanted variation of voltage Voutup to values greater than voltage Vref to cause an increase of potentialV309 up to a value greater than that of threshold Vcom or, in otherwords, to select a dynamic hysteresis value.

At time t53, the switching of the output of inverter I4 to the low statecauses the turning off of switch 407. Thus, from time t53, capacitor 403is charged by the current of current source 405.

Until a next time t54, the voltage across capacitor 403 is such thatsource 405 remains capable of delivering a constant current andpotential V309 is maintained at a value substantially equal, or evenequal, to value V2, as soon as the current delivered to node 309 bytransistor 301 remains lower than the current drawn from node 309 bytransistor 303 and current source 405.

At time t54, the voltage across capacitor 403 reaches a value such thatsource 405 is no longer capable of delivering a constant current, source405 for example delivering a lower and lower current from time t54. As aresult, from time t54, potential V309 tends to recover the value that itwould have had in the absence of elements 401, 403, 405, and 407.

At a next time t55, potential V309 recovers the value that it would havehad in the absence of elements 401, 403, 405, and 407 and then varies asif elements 401, 403, 405, and 407 were absent. In particular, in thisexample where voltage Vout remains lower than voltage Vref between timet51 and a time t58 subsequent to time t55 and where, at time t55,potential V309 has not reached a low or minimum value V3, potential V309decreases from time t55 to reach value V3 at a time t57 between timest55 and t58.

In the example of FIG. 5 , at a time t56 between times t55 and t57, thecircuit 19 of converter 1 starts an operating cycle as a response to thelow state of signal START. Thus, from time t56, voltage Vout increases.As long as voltage Vout remains lower than voltage Vref, potential V309remains pulled towards value V3, or even is equal to value V3.

In the example of FIG. 5 , at time t58, voltage Vout becomes equal toand then greater than voltage Vref. As a result, from time t58, thecurrent delivered to node 309 by transistor 301 becomes equal to andthen greater than the current drawn from node 309 by transistor 303, andthus the potential of node 309 increases and is progressively pulledtowards the potential of node 307.

Although this is not shown in the example of FIG. 5 , at a timesubsequent to time t58, the potential of node V309 becomes equal to andthen greater than threshold Vcom, which results, in the following order,in the switching of the output of inverter I1 to the low state, theturning off of switch 401, the switching of signal START to the highstate, and the turning on of switch 407.

An example where voltage Vout remains lower than voltage Vref betweentimes t51 and t56 has been described herein. However, as alreadyindicated, even if unwanted variations of voltage Vout result in voltageVout becoming greater than voltage Vref at times between time t52 andtime t54, due to potential V309 being pulled towards value V2 betweentimes t52 and t54, such variations do not cause a switching of signalSTART to the high state, provided for value V2 to be selectedsufficiently low with respect to the maximum values that voltage Voutcan take between times t52 and t54, the selection of value V2 beingwithin the abilities of those skilled in the art.

Further, in other examples, not shown, the circuit 19 of converter 1starts an operating cycle before time t54, whereby voltage Vout becomesgreater again than voltage Vref before time t54. In this case, from timet54, the potential of node 309 tends to recover the value that it wouldhave had in the absence of elements 401, 403, 405, and 407, that itreaches at time t55, even if this value is then greater than thresholdVcom. In this last case, between times t54 and t55, potential V309crosses threshold Vcom, whereby signal START switches to the high state.Thus, conversely to the already previously mentioned case of a statichysteresis comparator, signal START of comparator 400 switches sooner tothe high state.

An embodiment of comparator 400 where switches 401 and 407, capacitor403, and current source 405 first enable to confirm, when potential V309becomes smaller than the switching threshold of inverter I1, the lowstate of potential V309, and then to maintain the low state of signalSTART for a determined time period, has been described here-above inrelation with FIGS. 4 and 5 . In this embodiment, current source 405 isthen coupled, preferably connected, to node 305, to draw current fromnode 309.

In an alternative embodiment of comparator 400, switches 401 and 407,capacitor 403, and current source 405 first enable to confirm, when thepotential of node 309 becomes greater than the switching potential ofinverter I1, a high state of potential V309 and then to hold the highstate of signal START for a time period determined by the value of thecurrent delivered by current source 405 and by the value of capacitor403. The potential of node 309 here is said to be in the high state whenit is greater than the switching threshold of inverter I1. In thisvariation, the terminal of current source 405 opposite to capacitor 403is then coupled, preferably connected, to node 307, to deliver currentto node 309. Further, in this variation, switches 401 and 407 arepreferably each implemented by a PMOS transistor. In this variation,switch 401 is configured to turn on when the potential of node 309becomes greater than threshold Vcom, for example, when the output ofinverter I1 switches to the low state, and switch 407 is configured toturn off after the turning on of switch 401, for example, when signalSTART switches to the high state. In other words, the turning on ofswitches 401 and 407 results from a variation of the potential of node309 causing a switching of signal START from its low state to its highstate, that is, here, from a variation of the potential of node 309 tothe potential of node 307 during which the potential of node 309 crossesthe switching threshold of inverter I1.

The embodiment of comparator 400 described in relation with FIGS. 4 and5 and the above alternative embodiment may be combined. Comparator 400then comprises:

switch 401, capacitor 403, and current source 405 series-connectedbetween nodes 309 and 305;

switch 407 in parallel with capacitor 403;

an additional switch, an additional capacitor, and an additional currentsource series-connected between nodes 309 and 307; and

another additional switch in parallel with the additional capacitor. Thedetailed implementation of this combination is within the abilities ofthose skilled in the art based on the functional indications givenhere-above.

Embodiments and variations where the gain stage of comparator 400comprises four inverters in series between nodes 309 and 311 have beendescribed here-above. It will be within the abilities of those skilledin the art to modify the number of inverters in series between nodes 309and 311, preferably by providing an even number and/or a number greaterthan or equal to two inverters in series.

Further, although embodiments and variations where switch 401 iscontrolled by the output of an inverter of the gain stage of comparator400 have been described here-above, it may be provided for the switch tobe controlled by the output of an additional inverter which does notbelong to the gain stage and comprising an input coupled, respectivelyconnected, to node 309.

Although converter 1 has been described in the case where circuit 19orders the beginning of an operating cycle if signal START is in the lowstate, it will be within the abilities of those skilled in the art toadapt converter 1 to the case where circuit 19 orders the beginning ofan operating cycle if signal START is in the high state, particularly byinverting the inputs of the comparator having the respective voltageVref and Vout provided thereto.

Further, although the operation and the advantages of comparator 400have been illustrated in the case where it replaces the comparator 17 ofconverter 1, comparator 400 may be provided in others types ofconverters, and more generally in other electronic circuits, and mayhave the same advantages therein. For example, comparator 400 may beprovided in many systems where a first voltage representative of thevalue of an output quantity of the system is compared with a voltagerepresentative of a set point value of the output quantity of thesystem.

Various embodiments and variations have been described. It will beunderstood by those skilled in the art that certain features of thesevarious embodiments and variations may be combined, and other variationswill occur to those skilled in the art.

Finally, the practical implementation of the described embodiments andvariations is within the abilities of those skilled in the art based onthe functional indications given here-above. In particular, theimplementation of the non-illustrated portion of comparator 400 will bewithin the abilities of those skilled in the art based on the functionalindications given here-above, and different implementations can beenvisaged. For example, this non-illustrated portion may correspond to adifferential pair, each of transistors 301 and 303 enabling to copy acurrent flowing through one of the branches of the differential pair,or, in other words, the current flowing through one of transistors 301and 303 is an image of the current flowing through one of the branchesof the differential pair, the current flowing in the other one oftransistors 301 and 303 being an image of the current flowing throughthe other one of the branches of the differential pair.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. A voltage comparator comprising: an outputterminal; a first switch having a conduction terminal coupled to aninternal node, the internal node coupled to the output terminal; acurrent source; a capacitor; and a second switch coupled in parallelwith the capacitor, wherein the current source, the capacitor, and thefirst switch are series-connected, wherein the current source comprisesa first terminal coupled to the capacitor, and a second terminal coupledto a first node, the first node configured to receive a first voltage,and wherein the first switch is configured to turn on and the secondswitch is configured to turn off after the turning on of the firstswitch when a variation of an internal voltage of the internal nodetowards the first voltage causes a switching of an output voltage of theoutput terminal.
 2. The comparator of claim 1, further comprising afirst inverter having an input coupled, to the internal node and anoutput configured to control the first switch.
 3. The comparator ofclaim 2, wherein the first inverter is configured to control a turningon of the first switch after the variation of the internal voltagetowards the first voltage.
 4. The comparator of claim 2, furthercomprising a second inverter having an input coupled to the internalnode and an output coupled to the output terminal, wherein the output ofthe second inverter is configured to control the second switch.
 5. Thecomparator of claim 4, wherein the second inverter is configured tocontrol a turning off of the second switch after the variation of theinternal voltage towards the first voltage.
 6. The comparator of claim2, comprising a plurality of inverters coupled in series between theoutput of the first inverter and the output terminal.
 7. The comparatorof claim 1, wherein the comparator is configured to receive a firstinput voltage and a second input voltage, and wherein an internalvoltage of the internal node is representative of a comparison betweenthe first and second input voltages.
 8. A voltage comparator comprising:an output terminal; a first switch having a conduction terminal coupledto an internal node, the internal node coupled to the output terminal; acurrent source; a capacitor; and a second switch coupled in parallelwith the capacitor, wherein the current source, the capacitor, and thefirst switch are series-connected, wherein the current source comprisesa first terminal coupled to the capacitor, and a second terminal coupledto a first node, the first node configured to receive a first voltage,and wherein the first node is connected to ground.
 9. A voltagecomparator comprising: an output terminal; a first switch having aconduction terminal coupled to an internal node, the internal nodecoupled to the output terminal; a current source; a capacitor; a secondswitch coupled in parallel with the capacitor, wherein the currentsource, the capacitor, and the first switch are series-connected,wherein the current source comprises a first terminal coupled to thecapacitor, and a second terminal coupled to a first node, the first nodeconfigured to receive a first voltage; and first and second transistorsin series between the first node and a second node, the second nodeconfigured to receive a second voltage.
 10. The comparator of claim 9,wherein the comparator is configured to receive a power supply voltagebetween the first and second nodes, and wherein the first and secondtransistors are coupled to each other at the internal node.
 11. Thecomparator of claim 9, wherein the second voltage is higher than thefirst voltage.
 12. A voltage comparator comprising: an output terminal;a first switch having a conduction terminal coupled to an internal node,the internal node coupled to the output terminal; a current source; acapacitor; and a second switch coupled in parallel with the capacitor,wherein the current source, the capacitor, and the first switch areseries-connected, wherein the current source comprises a first terminalcoupled to the capacitor, and a second terminal coupled to a first node,the first node configured to receive a first voltage, and wherein thefirst voltage is a ground voltage, and wherein the first and secondswitches are metal-oxide semiconductor (MOS) transistors of the N-type,or wherein the first voltage is a power supply voltage, and wherein thefirst and second switches are metal-oxide semiconductor (MOS)transistors of the P-type.
 13. The comparator of claim 12, wherein thefirst voltage is a power supply voltage, and wherein the first andsecond switches are metal-oxide semiconductor (MOS) transistors of theP-type.
 14. A voltage converter comprising: an output stage; acomparator having a first input coupled to an output of the outputstage, a second input configured to receive a reference voltage, and anoutput; and a control circuit configured to control the output stagebased on the output of the comparator, the comparator comprising: afirst switch having a conduction terminal coupled to an internal node,the internal node coupled to the output of the comparator and configuredto have an internal voltage that is representative of a comparisonbetween the reference voltage and an input voltage at the first input ofthe comparator, a current source, a capacitor, and a second switchcoupled in parallel with the capacitor, wherein the current source, thecapacitor, and the first switch are series-connected.
 15. The converterof claim 14, further comprising an inductor coupled to the output of theoutput stage, wherein the converter is configured to generate an outputvoltage at an output node coupled to the inductor, and wherein the firstinput of the comparator is configured to receive the output voltage. 16.A method of operating a voltage comparator, the method comprising:receiving first and second input voltages; generating an internalvoltage at an internal node based on comparing the first and secondinput voltages; when the internal voltage has a first voltage that isdifferent from a threshold voltage, turning off a first transistorhaving a first conduction terminal coupled to the internal node, and acontrol terminal coupled to an output of a first inverter, the firstinverter having an input coupled to the internal node, and turning on asecond transistor having a first conduction terminal coupled to a secondconduction terminal of the first transistor, and a control terminalcoupled to the control terminal of the first transistor via a pluralityof inverters; when the internal voltage transitions from the firstvoltage to a second voltage, turning on the first transistor, whereinthe threshold voltage is between the first and second voltages; a firsttime after turning on the first transistor, turning off the secondtransistor; and generating an output voltage at an output terminal ofthe voltage comparator, the output terminal coupled to the controlterminal of the second transistor.
 17. The method of claim 16, whereinthe first time is based on a capacitance coupled between the firstconduction terminal of the second transistor and a second conductionterminal of the second transistor, and a current flowing through acurrent generator that is coupled to the capacitance.
 18. The method ofclaim 16, wherein the first voltage is higher than the second voltage.19. The method of claim 16, wherein a capacitor is coupled across thefirst and a second conduction terminals of the second transistor, andwherein a current source comprises a first terminal coupled to thecapacitor and the second transistor.
 20. The method of claim 19, whereinthe current source comprises a second terminal coupled to ground, andwherein a third transistor comprises a first conduction terminal coupledto the internal node, and a second conduction terminal coupled toground.